翻訳と辞書 Words near each other ・ Universal Transportes Aéreos ・ Universal Transverse Mercator coordinate system ・ Universal Truths and Cycles ・ Universal Tube & Rollform Equipment ・ Universal tuning ・ Universal Turing machine ・ Universal type ・ Universal Typeface Experiment ・ Universal Uclick ・ Universal United House of Prayer ・ Universal usability ・ Universal validity of collective labour agreements ・ Universal value ・ Universal variable formulation ・ Universal veil ・ Universal Verification Methodology ・ Universal village collaboration suite ・ Universal Waite tarot deck ・ Universal War ・ Universal War One ・ Universal Warning Records ・ Universal waste ・ Universal wavefunction ・ Universal Weather and Aviation ・ Universal White Brotherhood ・ Universal Windows Platform ・ Universal Wireless Communication Co., Inc. ・ Universal Wireless Communications Consortium ・ Universal Worship Service ・ Universal Wrestling Association Dictionary Lists mini英和辞書 mini和英辞書 Webster 1913 Latin-English FOLDOC Wikipedia English ウィキペディア

翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク Universal Verification Methodology ： ウィキペディア英語版 Universal Verification Methodology The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys. ==History== In December 2009, a technical subcommittee of Accellera — a standards organization in the electronic design automation (EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1),〔(Accellera Status )〕 a verification methodology developed jointly in 2007 by Cadence Design Systems and Mentor Graphics. On February 21, 2011, Accellera approved the 1.0 version of UVM.〔http://www.accellera.org/activities/vip〕 UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog base class library, and a User Guide.〔(Download from Accellera )〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Universal Verification Methodology」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.